![]() ![]() ![]() UUT : entity work.JK_Flipflop port map (clk,J,K,Q,Qbar,reset ) Signal clk,J,K,reset,Q,Qbar : std_logic := ' 0' ![]() The test bench program used for testing the design is given below: If (J =' 0' and K =' 0' ) then -No change in the outputĮlsif (J =' 0' and K =' 1' ) then -Set the output.Įlsif (J =' 1' and K =' 0' ) then -Reset the output. If (reset = ' 1' ) then -Reset the output. Signal qtemp,qbartemp : std_logic :=' 0' entity declaration with port definitionsĪrchitecture Behavioral of JK_Flipflop is ![]()
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